UPD44646187AF5-E30-FQ1-A中文资料瑞萨数据手册PDF规格书

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (15 x 17)

• HSTL interface

• DLL/PLL circuitry for wide output data valid window and future frequency scaling

• DDR read or write operation initiated each cycle

• Pipelined double data rate operation

• Separate data input/output bus

• Two-tick burst for low DDR transaction size

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two Echo clocks (CQ and CQ#)

• Data Valid pin (QVLD) supported

• Read latency : 2.5 clock cycles (Not selectable by user)

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 2.0 ns (500 MHz) for 2.5 clock cycles read latency

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port

• On-Die Termination (ODT) for better signal quality (Selectable ON/OFF by user)