UPD44644364AF5-E50-FQ1-A中文资料瑞萨数据手册PDF规格书

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (15 x 17)

• HSTL interface

• DLL/PLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Four-tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 20 μs after clock is resumed.

• User programmable impedance output (35 to 70 Ω)

• Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG 1149.1 compatible test access port