8,192 X 8 - BIT STATIC CMOS RAM

文件：280.23 Kbytes 页数：6 Pages

NEC

瑞萨

8,192 X 8 - BIT STATIC CMOS RAM

Renesas

瑞萨

MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • DLL/PLL circuitry for wide output data valid window and future frequency scaling • Pipelined double data rate operation • Common data input/output bus • Two-tick burst for low DDR transaction size • Two

文件：691.16 Kbytes 页数：38 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • DLL/PLL circuitry for wide output data valid window and future frequency scaling • Pipelined double data rate operation • Common data input/output bus • Two-tick burst for low DDR transaction size • Two

文件：691.16 Kbytes 页数：38 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • DLL/PLL circuitry for wide output data valid window and future frequency scaling • Pipelined double data rate operation • Common data input/output bus • Two-tick burst for low DDR transaction size • Two

文件：691.16 Kbytes 页数：38 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • DLL/PLL circuitry for wide output data valid window and future frequency scaling • Pipelined double data rate operation • Common data input/output bus • Two-tick burst for low DDR transaction size • Two

文件：691.16 Kbytes 页数：38 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • DLL/PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data

文件：683.76 Kbytes 页数：38 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • DLL/PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data

文件：683.76 Kbytes 页数：38 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • DLL/PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data

文件：683.76 Kbytes 页数：38 Pages

RENESAS

瑞萨

MOS INTEGRATED CIRCUIT

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • DLL/PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data

文件：683.76 Kbytes 页数：38 Pages

RENESAS

瑞萨