36M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data rat

文件：425.18 Kbytes 页数：35 Pages

RENESAS

瑞萨

Memory-QDRII/DDRII/ QDRII+/DDRII+ SRAM

Renesas

瑞萨

36M-BIT DDR II SRAM SEPARATE I/O 2-WORD BURST OPERATION

Features • 1.8 ± 0.1 V power supply • 165-pin PLASTIC BGA (15 x 17) • HSTL interface • PLL circuitry for wide output data valid window and future frequency scaling • Separate independent read and write data ports • DDR read or write operation initiated each cycle • Pipelined double data rat

文件：425.18 Kbytes 页数：35 Pages

RENESAS

瑞萨

Memory-QDRII/DDRII/ QDRII+/DDRII+ SRAM

Renesas

瑞萨