UPD44165084AF5-E50-EQ2-A中文资料瑞萨数据手册PDF规格书

Features

• 1.8 ± 0.1 V power supply

• 165-pin PLASTIC BGA (13 x 15)

• HSTL interface

• PLL circuitry for wide output data valid window and future frequency scaling

• Separate independent read and write data ports with concurrent transactions

• 100 bus utilization DDR READ and WRITE operation

• Four-tick burst for reduced address frequency

• Two input clocks (K and K#) for precise DDR timing at clock rising edges only

• Two output clocks (C and C#) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed.

• User programmable impedance output

• Fast clock cycle time : 3.3 ns (300 MHz) , 3.7 ns (270 MHz) , 4.0 ns (250 MHz) , 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

• Operating ambient temperature : Commercial TA = 0 to +70°C (-E33, -E40, -E50)

Industrial TA = –40 to +85°C (-E37Y, -E40Y, -E50Y)