UPD4164-3中文资料瑞萨数据手册PDF规格书

DESCRIPTION

The NEC /lPD4164 is a 65,536 words by 1 bit Dynamic N-Channel MOS RAM designed

to operate from a single +5V power supply. The negative-voltage substrate bias is

internally generated - its operation is both automatic and transparent.

The /lPD4164 utilizes a double-poly-layer N-channel silicon gate process which provides

high storage cell density, high performance and high reliability.

The /lPD4164 uses a single transistor dynamic storage cell and advanced dynamic

circuitry throughout, including the 512 sense amplifiers, which assures that power

dissipation is minimized. Refresh characteristics have been chosen to maximize yield

(low cost to user) while maintaining compatibility between Dynamic RAM generations.

The /lPD4164 three-state output is controlled by CAS, independent of RAS. After a

valid read or read-modify-write cycle, data is held on the output by holding CAS low.

The data out pin is returned to the high impedance state by returning CAS to a high

state. The /lPD4164 hidden refresh feature allows CAS to be held low to maintain

output data while RAS is used to execute RAS only refresh cycles.

Refreshing is accomplished by performing RAS only refresh cycles, hidden refresh

cycles, or normal read or write cycles on the 128 address combinations of AO through

A6 during a 2 ms period.

Multiplexed address inputs permit the /lPD4164 to be packaged in the standard 16

pin dual-in-line package. The 16 pin package provides the highest system bit densities

and is compatible with widely available automated handling equipment.

FEATURES

• High Memory Density

• MUltiplexed Address Inputs

• Single +5V Supply

• On Chip Substrate Bias Generator

• Access Time: /lPD4164-1 - 250 ns

/lPD4164-2 - 200 ns

/lPD4164-3 - 150 ns

• Read, Write Cycle Time: /lPD4164-1 - 410 ns

/lPD4164-2 - 335 ns

/lPD4164-3 - 270 ns

• Low Power Dissipation: 250 mW (Active); 28 mW (Standby)

• Non-Latched Output is Three-State, TTL Compatible

• Read, Write, Read-Write; Read-Modify-Write, RAS Only Refresh, and Page Mode

Capability

• All Inputs TTL Compatible, and Low Input Capacitance

• 128 Refresh Cycles (AO-A6 Pins for Refresh Address)

• CAS Controlled Output Allows Hidden Refresh

• Available in Both Ceramic and Plastic 16 Pin Packages