UPD30550中文资料VR5500™ 64-/32-BIT MICROPROCESSOR数据手册Renesas规格书

描述 Description

DESCRIPTION
The µPD30550 (VR5500) is a member of the VRSeries™ of RISC (Reduced Instruction Set Computer) microprocessors. It is a high-performance 64-/32-bit microprocessor that employs the RISC architecture developed by MIPS™.
The VR5500 allowsselection of a 64-bit or 32-bit bus width for the system interface, and can operate using protocols compatible with the VR5000 Series™ and VR5432™. FEATURES
• MIPS 64-bit RISC architecture
• High-speed operation processing
• Two-waysuperscaler super pipeline
• 300 MHz product:  603 MIPS
  400 MHz product:  804 MIPS
• High-speed translation lookaside buffer (TLB) (48 entries)
•Address space
• Physical:  36 bits (64-bit bus selected) 32 bits (32-bit bus selected)
• Virtual:  40 bits (in 64-bit mode) 31 bits (in 32-bit mode)
• On-chip floating-point unit (FPU)
• Supports sum-of-products instructions
• On-chip primarycache memory (instruction/data: 32 KB each)
• 2-wayset associative
• Supports line lock feature

特性 Features

• MIPS 64-bit RISC architecture
• High-speed operation processing
• Two-waysuperscaler super pipeline
• 300 MHz product:  603 MIPS
  400 MHz product:  804 MIPS
• High-speed translation lookaside buffer (TLB) (48 entries)
•Address space
• Physical:  36 bits (64-bit bus selected) 32 bits (32-bit bus selected)
• Virtual:  40 bits (in 64-bit mode) 31 bits (in 32-bit mode)
• On-chip floating-point unit (FPU)
• Supports sum-of-products instructions
• On-chip primarycache memory (instruction/data: 32 KB each)
• 2-wayset associative
• Supports line lock feature