UPD17072中文资料瑞萨数据手册PDF规格书

FEATURES

• 17K architecture: general-purpose register system

• Program memory (ROM)

6 KB (3072 ´ 16 bits): mPD17072

8 KB (4096 ´ 16 bits): mPD17073

• General-purpose data memory (RAM)

176 ´ 4 bits

• Instruction execution time

53.3 ms (with 75-kHz crystal resonator: normal operation)

106.6 ms (with 75-kHz crystal resonator: low-speed mode)

• Decimal operation

• Table reference

• Hardware for PLL frequency synthesizer

Dual modulus prescaler (230 MHz max.), programmable divider, phase comparator, charge pump

• Various peripheral hardware

General-purpose I/O ports, LCD controller/driver, serial interface, A/D converter, BEEP, intermediate frequency

(IF) counter

• Many interrupts

External: 1 channel

Internal: 2 channels

• Power-ON reset, CE reset, and power failure detector

• CMOS low power consumption

• Supply voltage: VDD = 1.8 to 3.6 V