UPD17015中文资料瑞萨数据手册PDF规格书

FEATURES

• 17K architecture : General registers

• Program memory (ROM) : 3K bytes (1528 ´ 16 bits)

• Data memory (RAM) : 97 ´ 4 bits

• General-purpose I/O ports : 12

• Minimum required peripheral hardware is built into the chip.

• LCD controller/driver : 9 segments ´ 4 commons

• PLL frequency synthesizer and 220-MHz (MAX.) prescaler

• Clock generator port

• Low-voltage operation : VDD = 1.8 to 3.6 V (TA = –10 to +50 °C)