UPD16638A中文资料瑞萨数据手册PDF规格书

FEATURES

· CMOS level input

· Output number selectable (300/309)

· Input of 6 bits (gradation data) by 3 dots

· Capable of outputting 64 values by means of 2 sets of 9 external power supplies (18 units) and a D/A converter

· Output dynamic range 8.3 Vp-p MIN. (@ VDD2 = 8.5 V)

· High-speed data transfer: fMAX. = 40 MHz (internal data transfer speed when operating at 3.0 V)

· Applicable for dot-line inversion, n-line inversion and column line inversion

· Single bank arrangement is possible (loaded with slim or bending TCP)