UPD160903中文资料瑞萨数据手册PDF规格书

FEATURES

• CMOS level input

• 384/402 outputs

• Input of 6 bits (gray-scale data) by 6 dots

• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter

• Logic power supply voltage (VDD1): 2.7 to 3.6 V

• Driver power supply voltage (VDD2): 5.5 V ± 0.275 V

• High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.7 V)

• Output dynamic range: VSS2 + 0.1 V to VDD2 – 0.1 V

• Apply for dot-line inversion, n-line inversion and column line inversion

• Output voltage polarity inversion function (POL)

• Display data inversion function (POL21, POL22)

• Single-side mounting is possible (incorporation of slim TCP)