UPD160061A中文资料瑞萨数据手册PDF规格书

FEATURES

• CMOS level input (2.3 to 3.6 V)

• 384 outputs

• Input of 6 bits (gray-scale data) by 6 dots

• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC)

• Logic power supply voltage (VDD1): 2.3 to 3.6 V

• Driver power supply voltage (VDD2): 7.5 to 9.5 V

• High-speed data transfer: fCLK = 65 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V)

40 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.3 V)

• Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V

• Apply for dot-line inversion, n-line inversion and column line inversion

• Output voltage polarity inversion function (POL)

• Input data inversion function (capable of controlling by each input port) (POL21, POL22)

• Apply for heavy load, light load

• Semi slim-chip shaped