UPD160040BN数据手册Renesas中文资料规格书

描述 Description

DESCRIPTION
The µPD160040B is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scale. Data input is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216 colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and even output pins respectively output gray-scale voltage of differing polarity.FEATURES
• CMOS level input
• 384 outputs
• Input of 8 bits (gray scale data) by 6 dots
• Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter
• Logic power supply voltage (VDD1): 2.5 to 3.6 V
• Driver power supply voltage (VDD2): 12.5 to 15.5 V (switchable, VSEL)
• Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V
• High-speed data transfer: fCLK. = 55 MHz MAX. (internal data transfer speed when operating at 3.0 V ≤ VDD1 ≤ 3.6 V)
                                    fCLK. = 40 MHz MAX. (internal data transfer speed when operating at 2.5 V ≤ VDD1 < 3.0 V)
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Output inversion function (POL21, POL 22)
• Output reset control is possible (MODE)
• Trough-rate control is possible (SRC)
• Output resistance control is possible (ORC)
• Single bank arrangement is possible (Loaded with slim TCP)

特性 Features

• CMOS level input
• 384 outputs
• Input of 8 bits (gray scale data) by 6 dots
• Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter
• Logic power supply voltage (VDD1): 2.5 to 3.6 V
• Driver power supply voltage (VDD2): 12.5 to 15.5 V (switchable, VSEL)
• Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V
• High-speed data transfer: fCLK. = 55 MHz MAX. (internal data transfer speed when operating at 3.0 V ≤ VDD1 ≤ 3.6 V)
                                    fCLK. = 40 MHz MAX. (internal data transfer speed when operating at 2.5 V ≤ VDD1 < 3.0 V)
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Output inversion function (POL21, POL 22)
• Output reset control is possible (MODE)
• Trough-rate control is possible (SRC)
• Output resistance control is possible (ORC)
• Single bank arrangement is possible (Loaded with slim TCP)