UCD9112集成电路（IC）的DC-DC开关控制器规格书PDF中文资料

UCD9112属于集成电路（IC）的DC-DC开关控制器。由德州仪器制造生产的UCD9112DC-DC 开关控制器PMIC（电源管理集成电路）DC 到 DC 开关式控制器是用于高效率电路的稳压 IC，其配置为生成高于（突升或步升）或低于（突降或步降）输入电源的输出电源电压。其他拓扑结构可能包括：降压-升压、反激、正激、Cuk、SEPIC、全桥、半桥和推挽式。这些器件不同于需要最小电压并“烧尽”多余电压的线性稳压器。

FEATURES

• Dual High Current Drivers.

• Full Compatibility with TI Fusion Digital Power

Supply Controllers, such as UCD91xx and

UCD92xx Families

• Operational to 2 MHz Switching Frequency

• High-Side FET and Output Current Limit

Protection with Independently Adjustable

Thresholds

• Fast High-Side Overcurrent Sense Circuit with

Fault Flag Output – Prevents Catastrophic

Current Levels on a Cycle-by-Cycle Basis

• Differential High-Gain Current Sense Amplifier

• Voltage Proportional to Load Current Monitor

Output

• Wide Input Voltage Range: 4.7 V to 15 V

Operation to 2.2 V Input Supported with an

External 4.5-6.5 V Bias Supply

• Onboard Regulated Supplies for Gate Drive

and Internal Circuits

• Integrated Thermal Shutdown

• Selectable Operation Modes:

– PWM plus Synchronous Rectifier Enable

(SRE) with Automatic Dead-Time Control

– Direct High-Gate and Low-Gate Inputs for

Direct FET Control

• 3-State PWM Input for Power Stage Shutdown

• UVLO Housekeeping Circuit

• Rated from –40°C to +125°C Junction

Temperature

APPLICATIONS

• Digitally-Controlled Synchronous-Buck Power

Stages for Single- and Multi-Phase

Applications

• Digitally-Controlled Power Modules

DESCRIPTION

The UCD7232 high current driver is specifically designed for digitally-controlled, point-of-load,

synchronous buck switching power supplies. Two

driver circuits provide high charge and discharge

current for the high-side NMOS switch and the

low-side NMOS synchronous rectifier in a

synchronous buck circuit. The MOSFET gates are

driven by an internally regulated VGG supply. The

internal VGG regulator can be disabled to permit the

user to supply their own gate drive voltage. This

flexibility allows a wide power conversion input

voltage range of 2.2 to 15 V. Internal under voltage

lockout (UVLO) logic insures VGG is good before

allowing chip operation.

A drive logic block allows operation in one of two

modes selected by the SRE Mode pin. In

Synchronous Mode, the logic block uses the PWM

signal to control both the high-side and low-side gate

drive signals. Dead time is automatically adjusted to

prevent cross conduction. The Synchronous Rectifier

Enable (SRE) pin controls whether or not the low-side

FET is turned on when the PWM signal is low. In

Independent Mode, the PWM and SRE pins control

the high-side and low-side gates directly. No

anti-cross-conduction logic is used in this mode.

On-board comparators monitor the voltage across the

high side switch and the voltage across an external

current sense element to safeguard the power stage

from sudden high current loads. Blanking delay is set

for the high side comparator by a single resistor in

order to avoid false reports coincident with switching

edge noise. In the event of a high-side fault or an

over-current fault, the high-side FET turned off and

the Fault Flag (FLT) is asserted to alert the digital

controller. The fault thresholds are independently set

by the HS Sense and ILIM pins.

Output current is measured and monitored by a

precision, high gain, switched capacitor differential

amplifier that processes the voltage present across

an external current sense element. The amplified

signal is available for use by the digital controller on

the IMON pin. The current sense amplifier has output

offset of 0.5 V so that both positive (sourcing) and

negative (sinking) current can be sensed.