UCD4076数据手册UTC中文资料规格书

描述 Description

The UTC UCD4076 are 4-bit registers consisting of D-typeflip-flops that feature 3-state outputs. Data Disable inputs areprovided to control the entry of data into the flip-flops. When bothData Disable inputs are low, data at the D inputs are loaded intotheir respective flip-flops on the next positive transition of theclock input. Output Disable inputs are also provided. When theOutput Disable inputs are both low, the normal logic states of thefour outputs are available to the load. The outputs are disabledindependently of the clock by a high logic level at either OutputDisable input, and present a high impedance.

特性 Features

Three-state outputs Input disabled without gating the clock Maximum input current of 1μA at 18Vtemperature range;100nA at 18V and 25°C1V at VDD=5V2V at VDD=10V2.5V at VDD=15V 5V,10V,and 15V parametric ratings