U74LVC1G80数据手册UTC中文资料规格书

描述 Description

The U74LVC1G80 is a single positive-edge-triggered D-typeflip-flop is designed for 1.65V to 5.5V VCC operation.When data at the data (D) input meets the setup timerequirement, the data is transferred to the  Q output on thepositive-going edge of the clock pulse. Clock triggering occurs at avoltage level and is not directly related to the rise time of the clockpulse. Following the hold-time interval, data at the D input can bechanged without affecting the level at the output.This device is fully specified for partial-power-down applicationsusing IOFF. The IOFF circuitry disables the outputs, preventingdamaging current backflow through the device when it is powereddown.

特性 Features

Operate from 1.65V to 5.5V Inputs accept voltages to 5.5V IOFF supports partial-power-down mode Low power dissipation: ICC=10μA (Max.) ±24mA output drive(VCC=3.3V)