SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

文件：192.74 Kbytes 页数：7 Pages

UTC

友顺

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

文件：192.74 Kbytes 页数：7 Pages

UTC

友顺

SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

文件：192.74 Kbytes 页数：7 Pages

UTC

友顺

Single D-type flip-flop; positive-edge trigger

DESCRIPTION The 74LVC1G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. FEATURES

文件：97.02 Kbytes 页数：18 Pages

PHI

PHI

Single D-type flip-flop; positive-edge trigger

1. General description The 74LVC1G79 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V

文件：275.95 Kbytes 页数：19 Pages

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