12-BIT ASYNCHRONOUS BINARY COUNTERS

The U74HC4040 is a 12-stage asynchronous binary counter witha clock input (CLK), an overriding asynchronous master reset input(CLR) and twelve parallel outputs (Q0 to Q11). The counteradvances on the High to Low transition of CLK. A HIGH on CLRclears all counter stages and forces all outputs Low, in Wide Operating Voltage Range of 4.5V to 5.5V Low Power Consumption, 8μA Maximum ICC ±4mA Output Drive at 5V;

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12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

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12-stage binary ripple counter

1. General description The 74HC4040; 74HCT4040 is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stage

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12-stage binary ripple counter

General description The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series. They are specified in compliance with JEDEC standard no. 7A. The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP), an overriding asynchr

文件：137.51 Kbytes 页数：24 Pages

PHI

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