U74HC273中文资料OCTAL D-TYPE FLIP-FLOPS WITH CLEAR数据手册UTC规格书

描述 Description

The U74HC273 devices are positive-edge-triggered D-typeflip-flops with a direct active low clear (CLR) input.Information at the data (D) inputs meeting the setup timerequirements is transferred to the Q outputs on the positive-goingedge of the clock (CLK) pulse. Clock triggering occurs at a particularvoltage level and is not related directly to the transition time of thepositive-going pulse. When CLK is at either the high or low level, theD input has no effect at the output.

特性 Features

Wide Operating Voltage Range of 2 V to 6 V Low Power Consumption, 80-μA Maximum ICCTypical tPD = 12 ns ±4mA Output Drive at 5 V Low Input Current of 1 μA Maximum Contain Eight Flip-Flops With Single-Rail Outputs Direct Clear Input Individual Data Input to Each Flip-Flop