1 Features

1• No Direction-Control Signal Needed

• Maximum Data Rates

– 24 Mbps (Push Pull)

– 2 Mbps (Open Drain)

• Available in the Texas Instruments NanoStar™

Package

• 1.65 V to 3.6 V on A Port and 2.3 V to 5.5 V on B

Port (VCCA ≤ VCCB)

• VCC Isolation Feature: If Either VCC Input Is at

GND, Both Ports Are in the High-Impedance State

• No Power-Supply Sequencing Required: Either

VCCA or VCCB Can Be Ramped First

• Ioff Supports Partial-Power-Down Mode Operation

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– A Port:

– 2500-V Human-Body Model (A114-B)

– 250-V Machine Model (A115-A)

– 1500-V Charged-Device Model (C101)

– B Port:

– 8-kV Human-Body Model (A114-B)

– 250-V Machine Model (A115-A)

– 1500-V Charged-Device Model (C101)

2 Applications

• I2C / SMBus

• UART

• GPIO

3 Description

This two-bit non-inverting translator is a bidirectional

voltage-level translator and can be used to establish

digital switching compatibility between mixed-voltage

systems. It uses two separate configurable powersupply

rails, with the A ports supporting operating

voltages from 1.65 V to 3.6 V while it tracks the VCCA

supply, and the B ports supporting operating voltages

from 2.3 V to 5.5 V while it tracks the VCCB supply.

This allows the support of both lower and higher logic

signal levels while providing bidirectional translation

capabilities between any of the 1.8-V, 2.5-V, 3.3-V,

and 5-V voltage nodes.

When the output-enable (OE) input is low, all I/Os are

placed in the high-impedance state, which

significantly reduces the power-supply quiescent

current consumption.

To ensure the high-impedance state during power up

or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is

determined by the current-sourcing capability of the

driver.

TXS0102DCUT属于集成电路（IC） > 转换器，电平移位器。美国德州仪器公司制造生产的TXS0102DCUT转换器，电平移位器逻辑转换器或电平移位器 IC 可用于在数字逻辑设备之间传递信息，这些设备可在不同/不兼容的供电电压下工作，或可实现不同的信令方式。例如，可以将需要 5 V 电源的数字输出传感器连接到具有 3.3 V I/O 电源的 FPGA，或者在 CMOS 或 TTL 等单端信令方式与 PECL 或 LVDS 等差分技术之间进行转换。