TUSB2036数据手册集成电路（IC）的控制器规格书PDF

描述 Description

The TUSB2036 hub is a 3.3-V CMOS device that provides up to three downstream ports in compliance with the USB 2.0 specification. Because this device is implemented with a digital state machine instead of a microcontroller, no firmware programming is required. Fully-compliant USB transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support both full-speed and low-speed devices by automatically setting the slew rate according to the speed of the device attached to the ports. The configuration of the BUSPWR pin selects either the bus-powered or the self-powered mode. The introduction of the DP0 pullup resistor disable pin, DP0PUR, makes it much easier to implement an onboard bus/self-power dynamic-switching circuitry. With the new function pin, the end-equipment vendor can reduce the total board cost while adding additional product value.

The EXTMEM (pin 26) enables or disables the optional EEPROM interface. When EXTMEM is high, the vendor and product IDs (VID and PID) use defaults, such that the message displayed during enumeration is General Purpose USB Hub.

The TUSB2036 supports both bus-powered and self-powered modes. External power-management devices, such as the TPS2044, are required to control the 5-V power source switching (on/off) to the downstream ports and to detect an overcurrent condition from the downstream ports individually or ganged.

An individually port power controlled hub switches power on or off to each downstream port as requested by the USB host. Also when an individually port power controlled hub senses an over-current event, only power to the affected downstream port will be switched off. A ganged hub switches on power to all its downstream ports when power is required to be on for any port. The power to the downstream ports is not switched off unless all ports are in a state that allows power to be removed. Also when a ganged hub senses an over-current event, power to all downstream ports will be switched off.

The logic level of the MODE pin controls the selection of a crystal input to drive an internal oscillator or an external clock source.

特性 Features

• Fully Compliant With the USB Specification as a Full-Speed Hub: TID #30220242
• Integrated USB Transceivers
• 3.3-V Low-Power ASIC Logic
• One Upstream Port and 2 or 3 Programmable Downstream Ports
• Total Number of Ports (2 or 3) Selected by Input Pin
• Total Number of Permanently Connected Ports Is Selected by 2 Input Pins

• Two Power Source Modes
• Self-Powered Mode
• Bus-Powered Mode

• All Downstream Ports Support Full-Speed and Low-Speed Operations
• Power Switching and Overcurrent Reporting Is Provided Ganged or Per Port
• Supports Suspend and Resume Operations
• Suspend Status Pin Available for External Logic Power Down
• Supports Custom Vendor ID and Product ID With External Serial EEPROM
• 3-State EEPROM Interface Allows EEPROM Sharing
• Push-Pull Outputs for PWRON Eliminate the Need for External Pullup Resistors
• Noise Filtering on OVRCUR Provides Immunity to Voltage Spikes
• Supports 6-MHz Operation Through a Crystal Input or a 48-MHz Input Clock
• Output Pin Available to Disable External Pullup Resister on DP0 for 3 ms After Reset or After Change on BUSPWR and Enable Easy Implementation of Onboard Bus/Self-Power Dynamic Switching Circuitry
• No Special Driver Requirements; Works Seamlessly With Any Operating System With USB Stack Support
• Available in 32-Pin HLQFP Package With a 0.8-mm Pin Pitch (JEDEC − S-PQFP-G For Low-Profile Quad Flat Pack)