TSC80C31-12ADR/P883中文资料Temic数据手册PDF规格书

描述 Description

The TSC80C31/80C51 is high performance SCMOS versions of the 8051 NMOS single chip 8 bit µC. The fully static design of the TSC80C31/80C51 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.

The TSC80C31/80C51 retains all the features of the 8051 : 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ; two 16 bit timers ; a 5-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits.

特性 Features

• Power control modes

• 128 bytes of RAM

• 4 K bytes of ROM (TSC80C31/80C51)

• 32 programmable I/O lines

• Two 16 bit timer/counter

• 64 K program memory space

• 64 K data memory space

• Fully static design

• 0.8 µm CMOS process

• Boolean processor

• 5 interrupt sources

• Programmable serial port

• Temperature range : commercial, industrial, automotive and military