TSB43EB42中文资料符合 IEEE 1394a-2000 标准的消费类电子产品解决方案数据手册TI规格书

描述 Description

The TSB43Ex42/43 is high-performance consumer electronics IEEE 1394 link layer and integrated physical layer devices designed for digitally interfacing advanced video consumer electronics applications. It supports formatting and transmission of IEC61883 data, including IEC61883-1 (general), IEC61883-2 (SD-DVCR), IEC61883-4 (MPEG2-TS), and IEC61883-7 (ITU-R BO.1294 SystemB-DSS). The TSB43Ex42/43 also supports standard IEEE 1394 data types, such as asynchronous, asynchronous streams, and PHY packets.
The TSB43EAxx/ECxx version incorporates DTCP (M6) baseline per the DTLA (5C) specification to support transmit and receive of up to two MPEG2 transport streams with encryption and decryption. The TSB43EAxx/ECxx version also includes hardware acceleration for content key generation.
The TSB43EBxx series are identical to the TSB43EAxx/ECxx series without implementation of the encryption/decryption features. The TSB43EB42/43 devices allow customers that do not require the encryption/decryption features to incorporate the TSB43Ex42/43 function without becoming DTLA licensees.
The TSB43Ex42/43 features an integrated 2-port/3-port PHY. The PHY operates at 100 Mbps, 200 Mbps, or 400 Mbps. They follow all requirements as stated in the IEEE 1394-1995 and IEEE 1394a-2000 standards.
Designing with this device may require extensive support. Before incorporating this device into a design, customers should contact TI or an Authorized TI Distributor.

特性 Features

• IEEE 1394 Features
• Compliant to IEEE Std 1394-1995 and IEEE Std 1394a-2000
• Separate Asynchronous ACK Buffers Decrease ACK-Tracking Burden on External CPU
• AES128 Encryption Support on HSDI Path (TSB43EC42/43 Only)
• Full or Restricted AKE Performed With Hardware Assist
• Localization Support Compliant With DTCP Draft Revision 1.51
• One Port Serial Only
• Packet Insertion – Two Insertion Buffers per HSDI for PAT, PMT, SIT, and DIT Packets
• External CPU Interfaces
• SRAM-Like 16-Bit Asynchronous Interface
• DMA
• Internal DMA Controller – Asynchronous, Asynchronous Stream TX/RX
• Auto Response DMA for SBP2 Transactions
• Data Buffers
• 2 × 2K-Byte Asynchronous/Asynchronous Stream Transmit Buffers
• 1 × 1K-Byte Self-ID Buffer
• Programmable Data/Space Available Indicators for Buffer Flow Control
• IEC61883-2 (SD-DVCR)
• IEC61883-7 (ITU-R BO.1294 System B) – DSS
• Asynchronous Packets
• PHY Packets (Including Self-IDs)
• Additional Features
• Unique \"Binding\" Method Protects Sensitive Data on the Circuit Board Traces at the External CPU Interface
• Unique \"EMI-AES Binding\" Method Prevents Protected Data From Being Transmitted in the Clear