TSB43AB21AIPDTEP集成电路（IC）的控制器规格书PDF中文资料

TSB43AB21AIPDTEP属于集成电路（IC）的控制器。由德州仪器制造生产的TSB43AB21AIPDTEP控制器该系列产品主要用于在采用不同通信协议和/或信令方法的端点之间提供信息连接。示例包括将 I2C 总线连接到 UART，将 USB 连接到 I2C、SPI、以太网或 UART、以太网 MAC 和 PHY 等的器件。此外，还包括用于通过为点对点通信设计的接口建立多路连接的器件，例如 USB 集线器控制器。

特性 Features

The TSB43AB21A-EP device supports the following features:

• Controlled Baseline

– One Assembly/Test Site, One Fabrication Site

• Extended Temperature Performance of –40°C to 85°C

• Enhanced Diminishing Manufacturing Sources (DMS) Support

• Enhanced Product-Change Notification

• Qualification Pedigree†

• Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1)

• Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus‡ and IEEE Std

1394a-2000

• Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394

• Compliant with Intel Mobile Power Guideline 2000

• Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed

concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume

• Power-down features to conserve energy in battery-powered applications include: automatic device power

down during suspend, PCI power management for link-layer, and inactive ports powered down

• Ultralow-power sleep mode

• One IEEE Std 1394a-2000 fully compliant cable port at 100M bits/s, 200M bits/s, or 400M bits/s

• Cable port monitors line conditions for active connection to remote node

• Cable power presence monitoring

• 1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

• Physical write posting of up to three outstanding transactions

• PCI burst transfers and deep FIFOs to tolerate large host latency

• PCI_CLKRUN protocol

• External cycle timer control for customized synchronization

• Extended resume signaling for compatibility with legacy DV components

• PHY-link logic performs system initialization and arbitration functions

• PHY-link encode and decode functions included for data-strobe bit level encoding

• PHY-link incoming data resynchronized to local clock

• Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, or 400M bits/s

• Node power class information signaling for system power management

• Serial ROM interface supports 2-wire serial EEPROM devices

• Two general-purpose I/Os

• Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std

1394a-2000 features

• Fabricated in advanced low-power CMOS process

• PCI and CardBus register support

• Isochronous receive dual-buffer mode

• Out-of-order pipelining for asynchronous transmit requests

• Register access fail interrupt when the PHY SCLK is not active

• PCI power-management D0, D1, D2, and D3 power states

• Initial bandwidth available and initial channels available registers

• PME support per 1394 Open Host Controller Interface Specification