TSB43AA82A中文资料用于 PC 外设的 2 端口高性能集成 PHY 和链路层芯片数据手册TI规格书

描述 Description

The TSB43AA82A is a high performance 1394 integrated PHY and link layer controller. It is compliant with the IEEE 1394-1995 and IEEE1394.a-2000 specifications and supports asynchronous transfers.

The TSB43AA82A has a generic 16/8-bit host bus interface. It supports parallel or multiplexed connections to the microcontroller (MCU) at rates up to 40 MHz.

The TSB43AA82A offers large data transfers with three mutually independent FIFOs: 1) the asynchronous command FIFO with 1512 Bytes, 2) the DMA FIFO with 4728 bytes and 3) the Config ROM/LOG FIFO with 504 bytes.

The features of the TSB43AA82A support the serial bus protocol 2 (SBP-2). It handles up to four initiators with the SBP-2 transaction manager. This SBP-2 transaction engine supports fully automated operation request block (ORB) fetches and fully automated memory page table fetches for both read and write transactions. Automated responses to other node requests are provided, this includes responding to another node’s read request to the Config ROM and issuing ack_busy_X for a single retry. Various control registers enable the user to program IEEE 1394 asynchronous transaction settings. The user can program the number of retries and the split transaction time out value by setting the time limit register in the CFR.

The TSB43AA82A also supports the direct print pProtocol (DPP). The Asynchronous Receive FIFO (ARF) in the TSB43AA82A is large enough to satisfy the connection register area, the DRF receiving FIFO can be used as the segment data unit (SDU) register to fulfill the large data transfer.

This document is not intended to serve as a tutorial on IEEE 1394; users are referred to IEEE Std 1394-1995 and IEEE 1394a-2000. (See Note 1).

特性 Features

• IEEE1394a-2000 Compliant
• Internal 1.8-V Circuit to Reduce Power Consumption
• Internal Voltage Regulator
• Automated Read Response for ConfigROM Register Access
• SBP–2 Related Functions:
• Automated Management ORB Fetching
• Automated PageTable Fetching
• Ability to Support Direct Print Protocol (DPP) Mode
• Auto Address Increment of Direct/Indirect Addressing on Data Transfer (Packetizer)
• 8/16 Bits Asynchronous and Synchronous DMA I/F With Handshake and Burst Mode
• 8/16 Bits Data/Address Multiplex Microcontroller and 8/16 Bits Separated Data/Address Bus
• Three FIFO Configurations That Support High Performance for the DMA and for Command Exchanges
Asynchronous Command FIFO:    1512 Bytes
ConfigROM/LOG FIFO:                 504 Bytes
DMA FIFO:                                  4728 Bytes

1IEEE Std 1394-1995 and IEEE 1394a–2000, IEEE Standard for a High Performance Serial Bus IEEE Std 1394a-2000, IEEE for a High Performance Serial Bus — Amendment 1