TSB41BA3A-EP中文资料增强型产品 Ieee 1394B 三端口电缆收发器/仲裁器数据手册TI规格书

描述 Description

The TSB41BA3A-EP provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41BA3A-EP interfaces with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It can also be connected via cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2.
The TSB41BA3A-EP is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL) from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals are separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes.

特性 Features

• Controlled Baseline
• Extended Temperature Performance of –40°C to 110°C
• Enhanced Product-Change Notification
• Fully Supports Provisions of IEEE 1394b-2002 at S100, S100B, S200, S200B, S400, and S400B Signaling Rates (B Signifies 1394b Signaling)
• Fully Interoperable With Firewire™, DTVLink, SB1394, DishWire, and i.LINK™ Implementation of IEEE Std 1394
• Same Three Fully Backward Compatible Ports Are 1394a-2000 Fully Compliant Cable Ports at 100/200/400 Mbps
• Arbitrated Short Reset
• Arbitration Acceleration
• Port Disable/Suspend/Resume
• Power-Down Features to Conserve Energy in Battery Powered Applications
• Fully Compliant With Open Host Controller Interface (OHCI) Requirements
• Cable Ports Monitor Line Conditions for Active Connection to Remote Node
• Data Interface to Link-Layer Controller Pin-Selectable From 1394a-2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (8 Parallel Bits at 98.304 MHz)
• Interoperable With Link-Layer Controllers Using 3.3-V Supplies
• Low-Cost 49.152-MHz Crystal Provides Transmit and Receive Data at 100/200/400 Mbps and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz
• Low-Cost, High-Performance, 80-Pin TQFP (PFP) Thermally Enhanced Package
• Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB41BA3A-EP Does Not Load the TPBIAS of Any Connected Device and Blocks Any Leakage From the Port Back to Power Plane
• Cable/Transceiver Hardware Speed and Port Mode Are Selectable by Pin States
• Supports Connection to S200 Plastic Optical Fiber Transceivers by Allowing Ports to be Forced to 1394b Beta-Only S200 Mbps and Beta-Only S100 Mbps
• Supports Use of 1394a Connectors by Allowing Ports 1 and 2 to Be Forced to 1394a-Only Mode

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thompson, Limited. i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation. FireWire is a trademark of Apple Computer, Inc. PowerPAD is a trademark of Texas Instruments.