TS5N412中文资料10V、2:1 (SPDT)、4 通道通用模拟开关数据手册TI规格书

描述 Description

The TS5N412 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the TS5N412 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The TS5N412 is a 4-bit 1-of-2 multiplexer/demultiplexer with a single output-enable (OE) input. The select (S) inputs control the data path of the multiplexer/demultiplexer. When OE is low, the multiplexer/demultiplexer is enabled and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the multiplexer/demultiplexer is disabled and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 3 Typ)
• Bidirectional Data Flow With Near-Zero Propagation Delay
• VCC Operating Range From 4.75 V to 5.25 V
• ESD Performance Tested Per JESD 22
• 1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications
• PCI Interface
• Memory Interleaving
• Low-Distortion Signal Gating