TPSI2140-Q1_V02中文资料德州仪器数据手册PDF规格书

1 Features

• Qualified for automotive applications

– AEC-Q100 grade 1: –40 to 125°C TA

• Integrated avalanche rated MOSFETs

– Designed and qualified for reliability during

overvoltage conditions, including system level

dielectric withstand testing (Hi-Pot)

• IAVA = 2-mA for 5-s pulses, 1-mA for 60-s

pulses

– 1200-V standoff voltage

– RON = 130-Ω (TJ = 25°C)

– TON, TOFF < 700-μs

• Low primary side supply current

– 9-mA ON state current

– 3.5-μA OFF state current

• Functional Safety Capable

– Documentation available to aid in ISO 26262

and IEC 61508 system design

• Robust isolation barrier:

– > 26 year projected lifetime at 1000-VRMS /

1500-VDC working voltage

– Isolation rating, VISO, up to 3750-VRMS / 5300-

VDC

– Peak surge, VIOSM, up to 5000-V

– ± 100-V/ns typical CMTI

• SOIC 11-pin (DWQ) package with wide pins for

improved thermal performance

– Creepage and clearance ≥ 8-mm (primarysecondary)

– Creepage and clearance ≥ 6-mm (across

switch terminals)

• Safety-related certifications

– (Planned) DIN VDE V 0884-11:2017-01

– (Planned) UL 1577 component recognition

program

2 Applications

• Solid state relay

• Hybrid, electric, and power train systems

• Battery Management Systems (BMS)

• Energy Storage Systems (ESS)

• Solar energy

• Onboard charger

• EV charging infrastructure

• See also the TI Reference Designs related to

these applications.

3 Description

The TPSI2140-Q1 is an isolated solid state

relay designed for high voltage automotive and

industrial applications. The TPSI2140-Q1 uses TI's

high reliability capacitive isolation technology in

combination with internal back-to-back MOSFETs to

form a completely integrated solution requiring no

secondary side power supply.

The primary side of the device is powered by only 9

mA of input current and incorporates a fail-safe EN

pin preventing any possibility of back powering the

VDD supply. In most applications, the VDD pin of

the device should be connected to a system supply

between 5 V–20 V and the EN pin of the device

should be driven by a GPIO output with logic HI

between 2.1 V–20 V. In other applications, The VDD

and EN pins could be driven together directly from

the system supply or from a GPIO output. All control

configurations of the TPSI2140-Q1 do not require

additional external components such as a resistor

and/or low side switch that are typically required in

photo relay solutions.

The secondary side consists of back-to-back

MOSFETs with a standoff voltage of ±1.2 kV from

S1 to S2. The TPSI2140-Q1 MOSFET's avalanche

robustness and thermally conscious package design

allow it to robustly support system level dielectric

withstand testing (HiPot) and DC fast charger surge

currents of up to 2 mA without requiring any external

components.