TPS7H3024-SP中文资料德州仪器数据手册PDF规格书

1 Features

• Radiation performance:

– Radiation hardness assurance (RHA) up to a

total ionizing dose (TID) of 100krad(Si)

– Single-event latchup (SEL), single-event

burnout (SEB), and single-event gate rupture

(SEGR) immune up to linear energy transfer

(LET) = 75MeV-cm2/mg

– Single-event functional interrupt (SEFI) and

single-event transient (SET) characterized up to

LET = 75MeV-cm2/mg

• Wide supply IN voltage range (VIN): 3V to 14V

• Monitor up to 4 voltage rails with high accuracy:

– TPS7H3024: 2 OV + 2 UV or 2 window with

push-pull RESETx

• Monitor coherent processor execution using the

watchdog timer

• Single resistor programmable global delay timer

• Programmable watchdog time-out

• Precision threshold voltage and hysteresis current:

– VTH_SENSEx of 599.7mV ± 1% across: voltage,

temperature, and radiation (TID)

– IHYS_SENSEx of 24μA ± 3% across: voltage,

temperature, and radiation (TID)

• Push-Pull outputs with programmable pull-up

voltage between 1.6V to 7V

– Global RESETx pull-up domain (VPULL_UP1)

– Common PWRGD and WDO pull-up domain

(VPULL_UP2)

• SR_UVLO input to reset all outputs

– Can also be utilized as configurable

undervoltage lockout with an external resistor

divider

• Available in military (–55°C to 125°C) temperature

range

2 Applications

• Satellite electrical power system (EPS)

• Monitoring voltage rails for complex digital

processors such as: FPGAs, SoCs, AFEs, and

power systems for space applications

• Monitoring of coherent processor execution

3 Description

The TPS7H3024-SP is an integrated, 3V to 14V, fourchannel

radiation-hardened power-supply supervisor

with watchdog. An accurate 599.7mV ± 1% threshold

voltage and a 24μA ± 3% hysteresis current

provide programmable monitoring voltages. A global

programmable delay timer is programmed via a single

resistor. Additionally, a PWRGD output is provided

to monitor the global power tree status. The device

also incorporates a positive edge detection watchdog

timer to monitor an external processor for coherent

execution. Faults can be detected and mitigated by

the external controller, using the SR_UVLO input.