TPS7A8701RTJRG4.A中文资料德州仪器数据手册PDF规格书

1 Features

1• Two Independent LDO Channels

• Low Output Noise: 3.8 μVRMS (10 Hz–100 kHz)

• Low Dropout: 100 mVMAX at 0.5 A

• Wide Input Voltage Range: 1.4 V to 6.5 V

• Wide Output Voltage Range: 0.8 V to 5.2 V

• High Power-Supply Ripple Rejection:

– 75 dB at DC

– 40 dB at 100 kHz

– 40 dB at 1 MHz

• 1.0% Accuracy Over Line, Load, and Temperature

• Excellent Load Transient Response

• Adjustable Start-Up In-Rush Control

• Selectable Soft-Start Charging Current

• Independent Open-Drain Power-Good (PGx)

Outputs

• Stable with a 10 μF or Larger Ceramic Output

Capacitor

• 4-mm × 4-mm, 20-Pin WQFN Package

2 Applications

• High-Speed Analog Circuits:

– VCOs, ADCs, DACs, LVDSs

• Imaging: CMOS Sensors, Video ASICs

• Test and Measurement

• Instrumentation and Medical

• Professional Audio

3 Description

The TPS7A87 is a dual, low-noise (3.8 μVRMS), lowdropout

(LDO) voltage regulator capable of sourcing

500 mA per channel with only 100 mV of maximum

dropout.

The TPS7A87 provides the flexibility of two

independent LDOs and approximately 30% smaller

solution size than two single-channel LDOs. Each

output is adjustable with external resistors from 0.8 V

to 5.2 V. The wide input-voltage range of the

TPS7A87 supports operation as low as 1.4 V and up

to 6.5 V.

With 1% output voltage accuracy (over line, load, and

temperature) and soft-start capabilities to reduce inrush

current, the TPS7A87 is ideal for powering

sensitive analog low-voltage devices [such as

voltage-controlled oscillators (VCOs), analog-to-digital

converters (ADCs), digital-to-analog converters

(DACs), complementary metal oxide semiconductor

(CMOS) sensors, and video application-specific

integrated circuits (ASICs)].

The TPS7A87 is designed to power noise-sensitive

components such as those found in instrumentation,

medical, video, professional audio, test and

measurement, and high-speed communication

applications. The very low 3.8-μVRMS output noise

and wideband PSRR (40 dB at 1 MHz) minimizes

phase noise and clock jitter. These features maximize

the performance of clocking devices, ADCs, and

DACs.