TPS74301RGWRM3中文资料德州仪器数据手册PDF规格书

1 Features

• Track Pin Allows for Flexible Power-Up

Sequencing

• 1% Accuracy Over Line, Load, and Temperature

• Supports Input Voltages as Low as 0.9V with

External Bias Supply

• Adjustable Output (0.8V to 3.6V)

• Ultra-Low Dropout:

– 55mV at 1.5A (typ)

• Stable with any output capacitor ≥ 2.2μF (new

chip)

• Stable with any or no Output Capacitor (legacy

chip)

• Excellent Transient Response

• Available in 5mm × 5mm × 1mm QFN and

DDPAK-7 Packages

• Open-Drain Power-Good

• Active High Enable

2 Applications

• Network attached storage - enterprise

• Rack servers

• Network interface cards (NIC)

• Merchant network and server PSU

3 Description

The TPS743 low-dropout (LDO) linear regulator

provides an easy-to-use robust power management

design for a wide variety of applications. The TRACK

pin allows the output to track an external supply. This

feature is useful in minimizing the stress on ESD

structures that are present between the CORE and

I/O power pins of many processors. The enable input

and power-good output allow easy sequencing with

external regulators. This complete flexibility allows the

user to configure a solution that meets the sequencing

requirements of FPGAs, DSPs, and other applications

with special start-up requirements.

A precision reference and error amplifier deliver 1%

accuracy over load, line, temperature, and process.

The device is stable with any type of capacitor greater

than or equal to 2.2μF. Each LDO is stable with lowcost

ceramic output capacitors and the family is fully

specified from –40°C to 125°C.