P-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the

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SUTEX

P- Channel Enhancement-Mode Vertical DMOS FETs

文件：562.77 Kbytes 页数：5 Pages

SUTEX

P- Channel Enhancement-Mode Vertical DMOS FETs

文件：562.77 Kbytes 页数：5 Pages

SUTEX

P-Channel Enhancement-Mode Vertical DMOS FET

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SUTEX

P-Channel Enhancement-Mode Vertical DMOS FETs

General Description\nThese low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input ► Low threshold — -2.0V max.\n► High input impedance\n► Low input capacitance\n► Fast switching speeds\n► Low on resistance\n► Free from secondary breakdown\n► Low input and output leakage\n► Complementary N- and P-channel devicesApplications\n► Logic level interfaces – ideal for TTL and CMOS\n► Sol;

Microchip

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