P-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the

文件：481.01 Kbytes 页数：4 Pages

SUTEX

P-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the

文件：481.01 Kbytes 页数：4 Pages

SUTEX

P-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the

文件：481.01 Kbytes 页数：4 Pages

SUTEX

P-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertexs well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the

文件：481.01 Kbytes 页数：4 Pages

SUTEX

P-Channel Enhancement Mode Vertical DMOS FETs

文件：711.37 Kbytes 页数：6 Pages

SUTEX

P-Channel Enhancement Mode Vertical DMOS FETs

文件：711.37 Kbytes 页数：6 Pages

SUTEX

P-Channel Enhancement Mode Vertical DMOS FETs

文件：639.78 Kbytes 页数：5 Pages

SUTEX

Photovoltaic Solar Cell Protection Schottky Diode

文件：373.92 Kbytes 页数：3 Pages

HY

虹扬科技

PHOTOVOLTAIC SOLAR CELL PROTECTION SCHOTTKY RECTIFIER

文件：142.4 Kbytes 页数：3 Pages

HY

虹扬科技

MOSFET, P-Channel Enhancement-Mode, -400V, 25 Ohm

This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature Low threshold (-2.4V max.) \nHigh input impedance \nLow input capacitance (60pF typical) \nFast switching speeds \nLow on-resistance \nFree from secondary breakdown \nLow input and output leakage;

Microchip

微芯科技