TP0604WG中文资料P-Channel Enhancement-Mode Vertical DMOS FETs数据手册Microchip规格书

描述 Description

Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown.

特性 Features

❏ Low threshold — -2.4V max.
❏ High input impedance
❏ Low input capacitance — 95pF typical
❏ Fast switching speeds
❏ Low on resistance
❏ Free from secondary breakdown
❏ Low input and output leakage
❏ Complementary N- and P-channel devicesApplications
❏ Logic level interfaces – ideal for TTL and CMOS
❏ Solid state relays
❏ Battery operated systems
❏ Photo voltaic drives
❏ Analog switches
❏ General purpose line drivers
❏ Telecom switches