TMS470R1A288中文资料德州仪器数据手册PDF规格书

FEATURES

· High-Performance Static CMOS Technology

· TMS470R1x 16/32-Bit RISC Core

(ARM7TDMI™)

– 24-MHz System Clock (48-MHz Pipeline)

– Independent 16/32-Bit Instruction Set

– Open Architecture With Third-Party

Support

– Built-In Debug Module

· Integrated Memory

– 288K-Byte Program Flash

– Two Banks With 8 Contiguous Sectors

– 16K-Byte Static RAM (SRAM)

– Memory Security Module (MSM)

– JTAG Security Module

· Operating Features

– Low-Power Modes: STANDBY and HALT

– Extended Industrial Temperature Range

· 470+ System Module

– 32-Bit Address Space Decoding

– Bus Supervision for Memory/Peripherals

– Digital Watchdog (DWD) Timer

– Analog Watchdog (AWD) Timer

– Enhanced Real-Time Interrupt (RTI)

– Interrupt Expansion Module (IEM)

– System Integrity and Failure Detection

– ICE Breaker

· Direct Memory Access (DMA) Controller

– 32 Control Packets and 16 Channels

· Zero-Pin Phase-Locked Loop (ZPLL)-Based

Clock Module With Prescaler

– Multiply-by-8 Internal ZPLL Option

– ZPLL Bypass Mode

· High-End Timer Lite (HET)

– 12 Programmable I/O Channels:

– 12 High-Resolution Pins

– High-Resolution Share Feature (XOR)

– High-End Timer RAM

– 64-Instruction Capacity

· External Clock Prescale (ECP) Module

– Programmable Low-Frequency External

Clock (CLK)

· Ten Communication Interfaces:

– Two Serial Peripheral Interfaces (SPIs)

– 255 Programmable Baud Rates

– Two Serial Communication Interfaces

(SCIs)

– 224 Selectable Baud Rates

– Asynchronous/Isosynchronous Modes

– Class II Serial Interface B (C2SIb)

– Normal 10.4 Kbps and 4X Mode 41.6

Kbps

– Two Standard CAN Controllers (SCC)

– 16-Mailbox Capacity

– Fully Compliant With CAN Protocol,

Version 2.0B

– Three Inter-Integrated Circuit (I2C) Modules

– Multi-Master and Slave Interfaces

– Up to 400 Kbps (Fast Mode)

– 7- and 10-Bit Address Capability

· 12-Channel 10-Bit Multi-Buffered ADC

(MibADC)

– 64-Word FIFO Buffer

– Single- or Continuous-Conversion Modes

– 1.55 μs Minimum Sample/Conversion Time

– Calibration Mode and Self-Test Features

· Flexible Interrupt Handling

· Expansion Bus Module (EBM) (PGE only)

– Supports 8- and 16-Bit Expansion Bus

Memory Interface Mappings

– 42 I/O Expansion Bus Pins

· 50 Dedicated General-Purpose I/O (GIO) Pins

and 43 Additional Peripheral I/Os (PGE)

· 14 Dedicated General-Purpose I/O (GIO) Pins

and 43 Additional Peripheral I/Os (PZ)

· 16 External Interrupts

· On-Chip Scan-Base Emulation Logic, IEEE

Standard 1149.1(1) (JTAG) Test-Access Port

· 144-Pin Plastic Low-Profile Quad Flatpack

(PGE Suffix)

· 100-Pin Plastic Low-Profile Quad Flatpack (PZ

Suffix)

(1) The test-access port is compatible with the IEEE Standard

1149.1-1990, IEEE Standard Test-Access Port and Boundary

Scan Architecture specification. Boundary scan is not

supported on this device.