SMARTDM™ Low-Power, Low-Voltage, 1.1-V to 3.6-V 1/0, 16-Bit, 26-KSPS Codec

1.1 Description The TLV320AIC13 implements the smart time division multiplexed serial port (SMARTDM). This design innovation optimizes the DSP performance with an advanced synchronous serial port in TDM format for glue-free interface to popular DSPs (i.e., C5x, C6x) and microcontrollers. The S

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德州仪器

Low Power CMOS, 16-Bit, 26-KSPS Codec With Smart Time Division Multiplexed (SMARTDM™) Serial Port

1.1 Description The TLV320AIC14 implements the smart time division multiplexed serial port (SMARTDM). This is TI’s design innovation to optimize DSP performance with its most advanced synchronous serial port in TDM format for glue-free interface to popular DSPs (i.e., C5x, C6x) and microcontro

文件：728.04 Kbytes 页数：58 Pages

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SMARTDM™ Low-Power, Low-Voltage, 1.1-V to 3.6-V 1/0, 16-Bit, 26-KSPS Codec

1.1 Description The TLV320AIC15 implements the smart time division multiplexed serial port (SMARTDM). This is TI’s design innovation to optimize DSP performance with its most advanced synchronous serial port in TDM format for glue-free interface to popular DSPs (i.e., C5x, C6x) and microcontro

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Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC

FEATURES · Stereo 16-Bit Oversampling Sigma-Delta A/D Converter · Stereo 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Sampli

文件：1.24218 Mbytes 页数：59 Pages

TI

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Layout and Grounding Guidelines for TLV320AIC2x

文件：983.6 Kbytes 页数：53 Pages

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德州仪器

Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC

文件：1.61033 Mbytes 页数：56 Pages

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PRODUCT NOTIFICATION

文件：330.63 Kbytes 页数：50 Pages

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低功耗立体声语音频带编解码器

The TLV320AIC2x is a low-cost, low-power, highly-integrated, high-performance, dual-voice codec. It features two 16-bit analog-to-digital (A/D) channels and two 16-bit digital-to-analog (D/A) channels, which can be connected to a handset, headset, speaker, microphone, or a subscriber line via a prog • Stereo 16-Bit Oversampling Sigma-Delta A/D Converter\n• Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock\n• Programmable Sampling Rate up to: \n• Max 104 Ksps With IIR/FIR Bypassed\n• On-Chip FIR Produced 84-dB SNR for ADC and 92-dB SNR for DAC over 1;

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丝印：320AIC20C；Package：TQFP(PFB)；Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC

FEATURES · Stereo 16-Bit Oversampling Sigma-Delta A/D Converter · Stereo 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Sampli

文件：1.24218 Mbytes 页数：59 Pages

TI

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丝印：320AIC20C；Package：TQFP(PFB)；Low-Power, Highly-Integrated, Programmable 16-Bit, 26-KSPS, Dual-Channel CODEC

FEATURES · Stereo 16-Bit Oversampling Sigma-Delta A/D Converter · Stereo 16-Bit Oversampling Sigma-Delta D/A Converter · Support Maximum Master Clock of 100 MHz to Allow DSPs Output Clock to be Used as a Master Clock · Selectable FIR/IIR Filter With Bypassing Option · Programmable Sampli

文件：1.24218 Mbytes 页数：59 Pages

TI

德州仪器