TLV320AIC11CPFB.A中文资料德州仪器数据手册PDF规格书

1.1 Features

• 16-bit oversampling sigma-delta A/D converter

• 16-bit oversampling sigma-delta D/A converter

• Maximum output conversion rate:

– 22 ksps with on-chip FIR filter

– 88 ksps with FIR bypassed

• Voiceband bandwidth in FIR-bypassed mode and final sampling rate at 8 ksps

– 90-dB SNR/ADC and 87-dB SNR/DAC with DSP’s FIR (FIR bypassed @ 88 ksps/5 V)

– 87-dB SNR/ADC and 85-dB SNR/DAC with DSP’s FIR (FIR bypassed @88 ksps/3.3 V)

• On-chip FIR produced 84-dB SNR for ADC and 85-dB SNR for DAC over 11-kHz BW

• Built-in functions including PGA, antialiasing analog filter, and operational amplifiers for general-purpose

interface (such as MIC interface and hybrid interface)

• Glueless serial port interface to DSPs (TI TMS320UC54x or standard DSPs)

• Automatic cascading detection (ACD) makes cascade programming simple and allows up to 8 devices to

be connected in cascade.

• On-fly reconfiguration modes include secondary-communication mode and direct-configuration mode (host

interface).

• Continuous data-transfer mode for use with autobuffering (ABU) to reduce DSP interrupt service overhead

• Event-monitor mode provides external-event control, such as RING/OFF-HOOK detection

• Programmable ADC and DAC conversion rate

• Programmable input and output gain control

• Separate software control for ADC and DAC power-down

• Low-voltage (DVDD1) 1.1-V to 3.6-V digital I/O

• Analog (AVDD1 and AVDD2) 3 V to 5.5 V core power supply

• Digital (DVDD2) 3 V to 5.5 V core power supply

• Power dissipation (PD) of 39 mW typical for 8-ksps at 3.3 V

• Hardware power-down mode to 0.2 mW

• Internal and external reference voltage (Vref)

• Differential and single-ended analog input/output

• 2s-complement data format

• Test mode, which includes digital loopback and analog loopback

• 600-Ω output driver