TLK10022CTR.A中文资料德州仪器数据手册PDF规格书

1.1 Features 1

• Automatic Digital Multiplexing/De-Multiplexing

of 4, 3, or 2 Independent Lower-Speed Gigabit

Serial Lines into a Single Higher-Speed Gigabit

Serial Line

• 4 x (0.25 to 2.5 Gbps) to 1 x (1 to 10 Gbps)

Multiplexing

• 3 x (0.5 to 3.33 Gbps) to 1x (1.5 to 10 Gbps)

• 2 x (0.5 to 5 Gbps) to 1 x (1 to 10 Gbps)

• 1 x (0.5 to 2.5 Gbps) to 1 x (0.5 to 2.5 Gbps)

• Programmable Per Channel Lane Switching

• Wide Data Rate Range for Multiple Application

Support

• Transmit De-Emphasis and Adaptive Receiver

Equalization on Both Low Speed and High

Speed Sides

• 8B/10B ENDEC Coding Support

• Raw (unencoded) Data Support

• Core Supply 1V; I/O: 1.5V/1.8V

• Programmable High Speed

Scrambling/Descrambling Functions Improve

Serial Link Transition Density and Reduce

Spectral Peaks

• Superior Signal Integrity Performance

• Low Power Operation: < 800mW per Channel

(typ)

• Flexible Clocking

• Multi Drive Capability (SFP+, backplane, cable)

• Support for Programmable Lane Marker

Character

• Support for Programmable HS/LS 10-Bit

Alignment Character

• Wide Range of Built-in Test Patterns

• 144-pin, 13mmx13mm FCBGA Package

1.2 Applications

• Gigabit Serial Link Aggregation

• Communications System Backplanes

• Machine Vision

• Video/Image Data Processing

1.3 Description

The TLK10022 is a dual-channel multi-rate link aggregator intended for use in high-speed bi-directional

point-to-point data transmission systems. The device allows for a reduction in the number of physical links

required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial

links.

Each channel of the TLK10022 has a low-speed interface which can accommodate one, two, three, or four

bidirectional serial links running at rates from 250 Mbps to 5 Gbps (maximum of 10 Gbps total throughput).

The device’s high speed interfaces (one per channel, bidirectional) can operate at rates from 1 Gbps to 10

Gbps. When a channel is configured for a certain multiplexing ratio (1-to-1, 2-to-1, 3-to-1, or 4-to-1), the

high speed side will operate at a fixed multiple of the low speed rate (e.g., four times faster for 4-to-1

mode) regardless of the number of lanes connected. Filler data will be placed on any unused lanes in

order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped

during normal operation without requiring a change in configuration.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data

type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted

over a single high-speed link. There is also a programmable scrambling/de-scrambling function available

to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition

density for clock recovery and DC balance over time) even for non-ideal input data.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed

and high speed are rate matched. The TX and RX datapaths are also independent, so the TX and RX can

operates in different modes (this excludes 3:1 mode which requires both the TX and RX path to run in the

same mode). This independence is restricted to using the same low speed line rate. For example, the TX

can operate at 4 x 2.5 Gbps while RX operates at 1 x 2.5 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided

they are operating at integer multiples. The High Speed line rate must be configured based on the fastest

Low Speed line rate.

The TLK10022 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane

de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with

integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive

receive equalization to help compensate for media impairments at higher frequencies. The device’s serial

transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as

PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10022 is capable of extracting clocking information from the

serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a

jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock

input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single

reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among

these are pattern generation and verification on all serial lanes as well as internal data loopback paths.