TLC7733QPWRQ1集成电路（IC）的监控器规格书PDF中文资料

TLC7733QPWRQ1属于集成电路（IC）的监控器。由美国德州仪器公司制造生产的TLC7733QPWRQ1监控器PMIC 监控器用于监视和/或控制电路中的电压轨，能够连接微控制器以维持一定的功率限值。监控器类型包括电池备用电路、监控器、多电压监控器、电源监控器、稳压器/监控器、复位计时器、定序器、简单复位/上电复位、智能开/关控制器、系统管理器、电压检测器和看门狗电路。

Qualified for Automotive Applications

Power-On Reset Generator

Automatic Reset Generation After

Voltage Drop

Precision Voltage Sensor

Temperature-Compensated Voltage

Reference

Programmable Delay Time by External

Capacitor

Supply Voltage Range . . . 2 V to 6 V

Defined RESET Output from VDD ≥1 V

Power-Down Control Support for Static

RAM With Battery Backup

Maximum Supply Current of 16 μA

Power Saving Totem-Pole Outputs

description

The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer

and microprocessor systems.

During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD (≥ 2 V) is established, the

circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE))

remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure

proper system reset. The delay time, td, is determined by an external capacitor:

td = 2.1 × 104 × CT

Where

CT is in farads

td is in seconds

Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed

SENSE threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold

voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage

and the delay time, td, has expired.

In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control

support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor

contains additional logic intended for control of static memories with battery backup during power failure. By

driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL

driven by the memory bank select signal (CSH1) of the microprocessor (see Figure 10), the memory circuit is

automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the

battery.)