THC63LVD104S中文资料112MHz 30Bits Color LVDS Receiver数据手册THine规格书

描述 Description

General Description
The THC63LVD104S receiver is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA resolutions. The THC63LVD104S converts the LVDS data streams back into 35bits of CMOS/TTL data with rising edge or falling edge clock for convenient with a variety of LCD panel controllers.At a transmit clock frequency of 112MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted at an effective rate of 784Mbps per LVDS channel.Using a 112MHz clock, the data throughput is 490Mbytes per second.

特性 Features

• Wide dot clock range: 8-112MHz suited for NTSC, VGA, SVGA, XGA, and SXGA
• PLL requires no external components
• 50% output clock duty cycle
• TTL clock edge and position programmable(3 step)
• Power down mode
• Low power single 2.5V CMOS design
• TQFP 64pin
• Pin compatible with THC63LVD104A
• Fail-safe for Open CLK Input