THC63LVD103数据手册集成电路（IC）的串行器解串器规格书PDF

描述 Description

General Description
The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for ris ing edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmit ted at an effective rate of 945Mbps per LVDS channel.

特性 Features

• Wide dot clock range: 8-135MHz suited for NTSC, VGA, SVGA, XGA,SXGA and SXGA+
• PLL requires no external components
• Supports spread spectrum clock generator
• On chip jitter filtering
• Clock edge selectable
• Supports reduced swing LVDS for low EMI
• Power down mode
• Low power single 3.3V CMOS design
• 64pin TQFP
• Backward compatible with THC63LVDM63R(18bits) / M83R(24bits)