TDP0604数据手册集成电路（IC）的信号缓冲器、中继器、分离器规格书PDF

描述 Description

The TDP0604 is a HDMI 2.0 redriver supporting data rates up to 6 Gbps. It is backwards compatible to HDMI 1.4b. The high-speed differential inputs and outputs can be either AC-coupled or DC-coupled which qualifies the TDP0604 to be used as a DP++ to HDMI level shifter or HDMI redriver.

The TDP0604 is a hybrid redriver supporting both source and sink applications. A hybrid redriver can operate either in a linear or limited redriver function. When configured as a limited redriver, the TDP0604 differential output voltage levels are independent of the graphics process unit (GPU) output levels ensuring HDMI compliant levels at the receptacle. The limited redriver mode is recommended for HDMI source applications. When configured as a linear redriver, the TDP0604 differential output levels are a linear function of the GPU output levels enabling TDP0604 to be transparent to link training and operate as a channel shortener. Linear redriver mode is recommended for HDMI sink applications.

The TDP0604 has an integrated HPD level shifter. The HPD level shifter will shift the 5-V HPD signal to either 1.8-V or 3.3-V. The level shifter output can also be configured for push, pull, or open-drain. Also integrated in the TDP0604 is a Digital Display Control (DDC) buffer. The DDC buffer offers capacitance isolation and level shifters 5-V DDC levels to as low as 1.2-V levels. The integration of the level shifter eliminates discrete solutions and thereby saves system cost.

The TDP0604 supports single power supply rails of 3.3-V on VCC and is offered in a commercial temperature ( TDP0604) and industrial temperature ( TDP0604I).

特性 Features

• AC-coupled or DC-coupled input and output supporting HDMI 2.0 data rates up to 6 Gbps
• Backwards compatible to HDMI 1.4b

• Supports dual-mode DisplayPort (DP++)
• Programmable receiver equalizer up to 12 dB at 3 GHz
• I2C or pin strap programmable
• Integrated HPD level shifter supporting both 1.8-V and 3.3-V LVCMOS levels
• Integrated DDC buffer supporting as low as 1.2-V levels
• Full lane swap on main lanes
• Digital display control (DDC) snooping function for link configuration
• Low power consumption:
• 6 Gbps active limited: 215 mW
• Power down (HPD_IN = L): 0.55 mW

• Available in commercial and industrial temperature
• Single 3.3-V power supply
• 40-pin, 0.4 mm pitch, 4 mm × 6 mm, WQFN package