TDA9143数据手册恩XP中文资料规格书

描述 Description

GENERAL DESCRIPTION
The TDA9143 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor with blanking
facilities for PALplus and EDTV-2 signals. The TDA9143 has been designed for use with baseband chrominance
delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL/NTSC comb filter.FEATURES
• Multi-standard colour decoder and sync processor for PAL, NTSC and SECAM
• PALplus helper blanking and EDTV-2 blanking
• I2C-bus controlled
• I2C-bus addresses hardware selectable
• Pin compatible with TDA9141
• Alignment free
• Few external components
• Designed for use with baseband delay lines
• Integrated video filters
• Adjustable luminance delay
• Noise detector with I2C-bus read-out
• Norm/no_norm detector with I2C-bus read-out
• CVBS or Y/C input, with automatic detection possibility
• CVBS output, provided I2C-bus address 8A is used
• Vertical divider system
• Two-level sandcastle signal
• VA synchronization pulse (3-state)
• HA synchronization pulse or clamping pulse CLP input/output
• Line-locked clock output (6.75 MHz or 6.875 MHz) or stand-alone I2C-bus output port
• Stand-alone I2C-bus input/output port
• Colour matrix and fast YUV switch
• Comb filter enable input/output with subcarrier frequency
• Internal bypass mode of external delay line for NTSC applications
• Low power standby mode with 3-state YUV outputs
• Fast blanking detector with I2C-bus read-out
• Blanked or unblanked sync on Youtby I2C-bus bit BSY
• Internal MACROVISION gating for the horizontal PLL enabled by bus bit EMG.

特性 Features

• Multi-standard colour decoder and sync processor for PAL, NTSC and SECAM
• PALplus helper blanking and EDTV-2 blanking
• I2C-bus controlled
• I2C-bus addresses hardware selectable
• Pin compatible with TDA9141
• Alignment free
• Few external components
• Designed for use with baseband delay lines
• Integrated video filters
• Adjustable luminance delay
• Noise detector with I2C-bus read-out
• Norm/no_norm detector with I2C-bus read-out
• CVBS or Y/C input, with automatic detection possibility
• CVBS output, provided I2C-bus address 8A is used
• Vertical divider system
• Two-level sandcastle signal
• VA synchronization pulse (3-state)
• HA synchronization pulse or clamping pulse CLP input/output
• Line-locked clock output (6.75 MHz or 6.875 MHz) or stand-alone I2C-bus output port
• Stand-alone I2C-bus input/output port
• Colour matrix and fast YUV switch
• Comb filter enable input/output with subcarrier frequency
• Internal bypass mode of external delay line for NTSC applications
• Low power standby mode with 3-state YUV outputs
• Fast blanking detector with I2C-bus read-out
• Blanked or unblanked sync on Youtby I2C-bus bit BSY
• Internal MACROVISION gating for the horizontal PLL enabled by bus bit EMG.