TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

1 Features Processor cores: • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceler

文件：5.00915 Mbytes 页数：251 Pages

TI

德州仪器

丝印：TDA4VE88；Package：FCBGA；TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

1 Features Processor cores: • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceler

文件：5.00915 Mbytes 页数：251 Pages

TI

德州仪器

丝印：TDA4VEN8J5AQ1；Package：FCBGA；TDA4VEN, TDA4AEN Jacinto™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Ar

文件：4.37703 Mbytes 页数：236 Pages

TI

德州仪器

丝印：TDA4VEN8K5AQ1；Package：FCBGA；TDA4VEN, TDA4AEN Jacinto™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Ar

文件：4.37703 Mbytes 页数：236 Pages

TI

德州仪器

丝印：TDA4VEN8K5AQ1；Package：FCBGA；TDA4VEN, TDA4AEN Jacinto™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Ar

文件：4.37569 Mbytes 页数：236 Pages

TI

德州仪器

TDA4VE TDA4AL TDA4VL Jacinto™ Processors, Silicon Revision 1.0

1 Features Processor cores: • Two C7x floating point, vector DSP, up to 1.0 GHz, 160 GFLOPS, 512 GOPS • Deep-learning matrix multiply accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist acceler

文件：5.00915 Mbytes 页数：251 Pages

TI

德州仪器

TDA4VEN, TDA4AEN Jacinto™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Ar

文件：4.37569 Mbytes 页数：236 Pages

TI

德州仪器

TDA4VEN, TDA4AEN Jacinto™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Ar

文件：4.37703 Mbytes 页数：236 Pages

TI

德州仪器

TDA4VEN, TDA4AEN Jacinto™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Ar

文件：4.37703 Mbytes 页数：236 Pages

TI

德州仪器

TDA4VEN, TDA4AEN Jacinto™ Processors

1 Features Processor Cores: • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4GHz – Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC – Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection • Single-core Ar

文件：4.33225 Mbytes 页数：234 Pages

TI

德州仪器