TDA2-17数据手册TI中文资料规格书

描述 Description

TI’s new TDA2x System-on-Chip (SoC) is a highly optimized and scalable family ofdevices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). TheTDA2x family enables broad ADAS applications in automobiles by integrating an optimal mix ofperformance, low power and ADAS vision analytics processing that aims to facilitate a moreautonomous and collision-free driving experience.
The TDA2x SoC enables sophisticated embedded vision technology in automobiles bybroadest range of ADAS applications including front camera, park assist, surround view and sensorfusion on a single architecture.
The TDA2x SoC incorporates a heterogeneous, scalable architecture that includes a mixof TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation cores, VisionAccelerationPac, ARM Cortex-A15 MPCore™ and dual-Cortex-M4 processors. The integration of a videoaccelerator for decoding multiple video streams over an Ethernet AVB network, along with graphicsaccelerators for rendering virtual views, enable a 3D viewing experience. And the TDA2x SoC alsointegrates a host of peripherals including multi-camera interfaces (both parallel and serial) forLVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.
The Vision AccelerationPac for this family of products includes multiple embeddedvision engines (EVEs) offloading the vision analytics functionality from the application processorwhile also reducing the power footprint. The Vision AccelerationPac is optimized for visionprocessing with a 32-bit RISC core for efficient program execution and a vector coprocessor forspecialized vision processing.
Additionally, TI provides a complete set of development tools for the ARM, DSP, and EVEcoprocessor, including C compilers, a DSP assembly optimizer to simplify programming andscheduling, and a debugging interface for visibility into source code execution.
The TDA2x ADAS processor is qualified according to the AEC-Q100 standard.

特性 Features

• Architecture Designed for ADAS Applications
• Video, Image, and Graphics Processing Support
• Full-HD Video (1920 × 1080p, 60fps)
• Multiple Video Input and Video Output

• ARM® Cortex®-A15 Microprocessor Subsystem

• Up to 2 C66x Floating-Point VLIW DSP
• Fully Object-Code Compatible With C67x and C64x+

• Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle

• Up to 2.5MB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• DDR2/DDR3/DDR3L Memory Interface (EMIF) Module
• Supports up to DDR2-800 and DDR3-1066

• Up to 2GB Supported
• Dual ARM® Cortex®-M4 Image Processing Units (IPU)
• Vision AccelerationPac
• Upto Two Embedded Vision Engines (EVEs)

• IVA-HD Subsystem
• Display Subsystem
• Display Controller With DMAEngine and Three Pipelines
• HDMI™ Encoder: HDMI 1.4a and DVI 1.0Compliant

• 2D-Graphics Accelerator (BB2D) Subsystem
• Vivante™ GC320Core

• Video Processing Engine (VPE)
• Dual-Core PowerVR® SGX544™ 3D GPU

• Two Video Input Port (VIP) Modules
• Support for up to 7Multiplexed Input Ports


• General-Purpose Memory Controller (GPMC)

• Enhanced Direct Memory Access (EDMA) Controller

• 2-Port Gigabit Ethernet (GMAC)
• Dual Controller Area Network (DCAN) Modules
• CAN 2.0BProtocol

• PCI-Express 3.0 Port With Integrated PHY
• Single Port With 1 Lane at 5.0 Gbps

• Sixteen 32-Bit General-Purpose Timers

• 32-Bit MPU Watchdog Timer

• Ten Configurable UART/IrDA/CIR Modules

• Four Multichannel Serial Peripheral Interfaces (McSPI)
• Quad SPI Interface (QSPI)

• Five Inter-Integrated Circuit (I2C) Ports

• Seven Multichannel Audio Serial Port (McASP) Modules

• Three High-Speed USB 2.0 Dual-Role Devices
• Three MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
• Up to 247 General-Purpose I/O (GPIO) Pins

• Real-Time Clock Subsystem (RTCSS)
• Device security features
• Hardware Crypto accelerators and DMA

• Firewalls
• JTAG® lock
• Secure keys
• SecureROM and boot

• Power, Reset, and Clock Management

• On-Chip Debug With CTools Technology
• Automotive AEC-Q100 Qualified
• 28-nm CMOS Technology

• 17 mm × 17 mm, 0.65-mm Pitch, 625-Pin BGA (AAS)
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