TCP630-10R中文资料TEWS数据手册PDF规格书

Application Information

The TCP630 is a standard 3U 32 bit CompactPCI module providing a user configurable FPGA with 300,000 or 600,000 system gates. All local signals from the PCI controller are routed to the FPGA.

The TCP630 provides 64 ESD-protected TTL lines, 32 differential I/O lines using EIA-422 / EIA-485 compatible, ESD-protected line transceivers or 32 TTL and 16 differential I/Os. All lines are individually programmable as input, output or tri-state. The receivers are always enabled, which allows determining the state of each I/O line at any time. This can be used as read back function for lines configured as outputs. Each TTL I/O line has a pull-up resistor. The pull-up voltage is selectable to be either +3.3V or +5V. The differential I/O lines are terminated by 120Ω resistors.

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For flexible front I/O solutions the TCP630 provides a PIM Module slot, allowing active and passive signal conditioning. With the TPIM003 all I/O signals are provided on a HD68 connector. An option also offers in parallel rear I/O via the J2 connector.

TCP630-10R

The FPGA is configured by a serial flash. The flash device is in-system programmable via driver software over the PCI bus. An in-circuit debugging option is available via an optionally mountable JTAG header for readback and real-time debugging of the FPGA design (using Xilinx “ChipScope”).

A programmable clock generator supplies up to six different clock frequencies between 200 kHz and 166 MHz. All outputs are available at the FPGA, one clock source is in addition used as the local clock signal for the PCI controller. The clock generator settings are stored in an EEPROM and can be changed by the driver software through PCI9030 GPIO pins.

The configuration EEPROM of the PCI controller can also be modified by the driver software, to adapt address spaces etc.

User applications can be developed using the design software ISE WebPACK which can be downloaded free of charge from www.xilinx.com.

For First Time Users the Engineering Documentation TCP630-ED is recommended. The Engineering Documentation includes TCP630-DOC, schematics, data sheets / application notes of the components and well documented sample VHDL source code.

Software Support (TDRV004-SW-xx) for different operating systems is available.