CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip-Flop with Preset and Clear

文件：313.61 Kbytes 页数：10 Pages

TOSHIBA

东芝

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：287.67 Kbytes 页数：7 Pages

TOSHIBA

东芝

74HC CMOS logic IC series

Function：Dual J-~K Flip-Flop with Preset and Clear\nNumber of Circuits：2\nRoHS Compatible Product(s) (#)：Available\nAssembly bases：日本

Toshiba

东芝

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

文件：65.67 Kbytes 页数：9 Pages

PHI

飞利浦

High Speed CMOS Logic

文件：643.32 Kbytes 页数：6 Pages

SS

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

文件：271.64 Kbytes 页数：16 Pages

NEXPERIA

安世