TC74HC107AF中文资料东芝数据手册PDF规格书

Dual J-K Flip Flop with Clear

The TC74HC107A is a high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

In accordance with the logic levels applied to the J and K inputs, the outputs change state on the negative going transition of the clock pulse.

CLR is independent of the clock and is accomplished by a low logic level on the input.

All inputs are equipped with protection circuits against static discharge or transient excess voltage.

Features

• High speed: fmax = 75 MHz (typ.) at VCC = 5 V

• Low power dissipation: ICC = 2 μA (max) at Ta = 25°C

• High noise immunity: VNIH = VNIL = 28 VCC (min)

• Output drive capability: 10 LSTTL loads

• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)

• Balanced propagation delays: tpLH ∼ − tpHL

• Wide operating voltage range: VCC (opr) = 2~6 V

• Pin and function compatible with 74LS107