TC5588P-25中文资料东芝数据手册PDF规格书

Description

The TC5588P/J is a 65,536 bit high speed CMOS static random access memory organized as 8,192 words by 8 bits and operated

from a single 5V supply. Toshiba's advanced CMOS technology and circuit design enable high speed operation.

The TC5588P/J features low power dissipation when the device is deselected using chip enable (CE1, CE2) and has an output

enable input (OE) for fast memory access. Also, the device power between memory accesses is reduced by an automatic power

down circuit.

The TC5588P/J is suitable for use in high speed applications such as cache memory and high speed storage. All inputs and

outputs are TTL compatible. The TC5588P/J is available in a 300mil width, 28-pin DIP and SOJ suitable for high density surface

assembly.

Features

Fast access time

TC5588P/J-15

TC5588P/J-20

TC5588P/J-25

-

15ns (max.)

20ns (max.)

25ns (max.)

35ns (max.)

- TC5588P/J-35

• Low power dissipation

- Operation:

- TC5588P/J-15

- TC5588P/J-20

- TC5588P/J-25

- TC5588P/J-35

- Standby:

135mA (max.)

115mA (max.)

115mA (max.)

115mA (max.)

1mA (max.)

• Single 5V power supply: 5V±10

• Fully static operation

• Inputs and outputs TTL compatible

• Output buffer control: OE

• Package:

- TC5588P: DIP28-P-300B

- TC5588J: SOJ28-P-300A