TC518129APL-10中文资料东芝数据手册PDF规格书

Description

The TC518129A is a 1M bit high speed CMOS pseudo static RAM organized as 131,072 words by 8 bits. The TC518129A utilizes

a one transistor dynamic memory cell with CMOS peripheral circuitry to provide high capacity, high speed and low power storage. The

TC518129A operates from a single 5V power supply. Refreshing is supported by a refresh (RFSH) input which enables two types of

refreshing-auto refresh and self refresh. The TC518129A features a static RAM-like interface with a write cycle in which the input

data is written into the memory cell at the rising edge of R/WW thus simplifying the microprocessor interface.

A CS standby mode interface is incorporated in the TC518129A family, with the CE2 pin in the TC518128A family changed to a

CS pin. The TC518129A is available in a 32-pin, 0.6 inch and 0.3 inch width plastic DIP, a small outline plastic flat package, and a

32-pin thin small outline plastic package (forward type).

Features

• Organization: 131,072 words x 8 bits

• Single 5V power supply

Fast access time

CEA CE Access Time

TOEA OE Access Time

tac Cycle Time

Power Dissipation

Self Refresh Current

TC518129A Family

-80

-10

80ns

100ns

35ns

40ns

130ns

160ns

385mW 330mW

- TC518129AP/APL

TC518129AF/AFL

-

- TC518129ASP/ASPL

- TC518129AFW/AFWL

- TC518129AFTL

-12

120ns

50ns

190ns

275mW

1mA/200µA (L version)

• Auto refresh is supported by an internal refresh address counter

• Self refresh is supported by an internal timer

Inputs and outputs TTL compatible

Refresh: 512 refresh cycles 8ms

• Auto refresh power down feature

• Package

: DIP32-P-600

: SOP32-P-450

: : DIP32-P-300

: SOP32-P-525

: TSOP32-P-0820